Lesson 11: The End of Moore's Law & Chiplet Packaging

Introduction: when transistors cannot get any smaller

For 5 decades, Moore's law (transistor count per die doubling every ~2 years) was the hidden engine behind EVERY earlier lesson in this series — deeper pipelines (Lesson 4), bigger caches (Lesson 7), more elaborate out-of-order machinery (Lesson 6) all needed MORE transistors to build. But shrinking transistors is now hitting genuine PHYSICAL limits — and the chip industry found its way out not by shrinking further, but by ASSEMBLING differently.

1. Silicon's physical limits & the end of Moore's law

Once the transistor gate shrinks below 3nm, electrons start "tunnelling through" the thin insulating layer via quantum tunnelling — this leakage current is NOT a design flaw but an unavoidable physical consequence of distances approaching atomic scale. At the same time, packing transistors more densely concentrates heat to the point where the whole die CANNOT be switched on at full clock at once without burning the chip — the phenomenon of Dark Silicon (the silicon that must stay off, or run slow, to keep temperatures safe).

Node (nm)   Nam gioi thieu (~)   Ghi chu
180          1999                 Con thoai mai, chua co van de ro ret
65           2006                 Bat dau xuat hien dong ro ri (leakage) dang ke
14           2014                 FinFET pho bien - kiem soat kenh dan tot hon
5            2020                 Hieu ung luong tu bat dau anh huong ro ret
3 va nho hon 2023+                Quantum tunneling + Dark Silicon la rao can CHINH
                                   -> chuyen huong sang chiplet + toi uu vi kien truc

2. The chiplet design trend

Instead of fabricating ONE enormous die holding everything (CPU, I/O, cache), a Chiplet design splits it into SEVERAL smaller dies, each with its own role (CPU cores, the I/O controller, a large cache…) — then assembles them on an interposer (an intermediate connecting substrate). AMD Ryzen, Intel Meteor Lake and Apple M-Ultra all use this strategy.

Monolithic (1 die lon, mot khoi nguyen ven):
  +------------------------------------------+
  |  CPU cores | Cache lon | Bo dieu khien IO |
  +------------------------------------------+
  MOT loi chi tiet nho o BAT KY dau -> CA DIE hong -> ty le hong CAO voi die lon

Chiplet (nhieu die nho ghep tren interposer):
  +--------+  +--------+  +--------+  +--------+
  | CPU die|  | CPU die|  | IO die |  |Cache die|
  +--------+  +--------+  +--------+  +--------+
        \\        |            |          /
         +-------+-- Interposer (nen ket noi) --+
  MOI die nho rieng - loi 1 die CHI hong die DO, khong keo theo ca he thong

That "can eat significantly" deserves a number, because it is the counterweight to all the cost savings section 4 is about to compute. If a local access costs 1 ns and one crossing to another die costs 4 ns, the average latency depends only on the fraction of accesses that leave the die:

// 30% of accesses land on another die (a poorly partitioned workload)
crossDieLatency(1, 4, 0.3);
// -> { avg: 1.9 ns, slowdown: 1.90 }   nearly twice as slow as monolithic

// The same hardware, but partitioned so only 5% of accesses cross a die
crossDieLatency(1, 4, 0.05);
// -> { avg: 1.15 ns, slowdown: 1.15 }  the penalty almost disappears

// Identical silicon, identical interposer. Only the partitioning changed.

3. 3D IC packaging & TSV interconnects

Beyond assembling SIDEWAYS (chiplets next to each other on an interposer), 3D IC technology STACKS silicon VERTICALLY, connecting the layers with TSV (through-silicon vias — conducting holes bored through the silicon). Real examples: AMD's 3D V-Cache (an extra SRAM cache layer stacked directly ON TOP of the CPU die) and HBM (high bandwidth memory) stacked right beside the GPU — maximising both capacity AND interconnect bandwidth within the same board area.

4. Computing yield rate & manufacturing cost

A round silicon wafer is cut into many square dies — but NOT every die comes out defect-free. Yield (the proportion that pass) falls as die area GROWS, because a larger die is likelier to catch at least 1 random defect on the wafer surface. The Poisson model (simple, somewhat pessimistic) and the Murphy one (more realistic) both express this relationship:

$$Y_{Poisson} = e^{-A \times D} \qquad\qquad Y_{Murphy} = \left(\frac{1 - e^{-A \times D}}{A \times D}\right)^2$$

where $A$ = die area (mm²) and $D$ = defect density (defects/mm²). Verified for real: a 300mm wafer (the industry standard) at a defect density of 0.001 defects/mm² — a monolithic die of 600mm² yields only 90 die/wafer, with a Murphy yield of just 56,55%. Split into 4 chiplet 150mm² (the SAME total logic as the big die) yields 416 die/wafer — nearly 5 times as many — with yield leaping to 86,23%.

function yieldMurphy(area, defectDensity) {
  const x = area * defectDensity;
  return Math.pow((1 - Math.exp(-x)) / x, 2);
}
function diesPerWafer(waferDiameterMm, dieAreaMm2) {
  const waferArea = Math.PI * Math.pow(waferDiameterMm / 2, 2);
  const edgeLoss = (Math.PI * waferDiameterMm) / Math.sqrt(2 * dieAreaMm2);
  return Math.floor(waferArea / dieAreaMm2 - edgeLoss);
}
function costPerGoodDie(waferCostUsd, dieAreaMm2, waferDiameterMm, defectDensity, yieldFn) {
  return waferCostUsd / (diesPerWafer(waferDiameterMm, dieAreaMm2) * yieldFn(dieAreaMm2, defectDensity));
}
// Verified: diesPerWafer(300, 600) = 90;  diesPerWafer(300, 150) = 416
// Verified: yieldMurphy(600, 0.001) = 0,5655;  yieldMurphy(150, 0.001) = 0,8623

At a wafer price of 10,000 USD (an illustrative figure): the cost of ONE good monolithic die is ~ 196,49 USD. The cost of getting all 4 good chiplets (exactly 1 finished product, the same total logic as the big die) is only ~111,51 USD — 43% cheaper. That is the powerful economic force pushing the chip industry towards chiplets.

const costMono = costPerGoodDie(10000, 600, 300, 0.001, yieldMurphy);       // ~196,49 USD
const costChiplet1 = costPerGoodDie(10000, 150, 300, 0.001, yieldMurphy);   // ~27,88 USD/chiplet
const costChiplet4 = costChiplet1 * 4;                                      // ~111,51 USD (can 4 chiplet)
// Verified: costChiplet4 (111,51) < costMono (196,49) - re hon dung 43%

5. The full bill: why small chips stay monolithic

The "43% cheaper" figure just computed needs one thing spelled out: it counts only the silicon. But chiplets pay costs a monolithic die simply does not have:

• The interposer — itself another piece of silicon, which has to be manufactured and has a price of its own.
• Testing each die before assembly — this is the known-good dieproblem: put one bad die into the package and the whole package is ruined, taking every good die already in it down with it. So each piece must be tested separately first, and every test costs money.
• Assembly risk — the multi-piece assembly step has its own failure rate, and a failed package means writing off all the good silicon inside it.

Put all three into the same 600mm² problem from section 4:

// Monolithic 600mm2: no interposer, simple packaging, 99% package yield
// -> silicon 196.49 + packaging 3.00  = 201.51 USD

// Chiplet 4 x 150mm2: interposer 15, test + assembly 3/die, 97% package yield
// -> silicon 111.51 + packaging 27.00 = 142.79 USD

// Real saving: 29%, not 43%. Packaging is 19.5% of the chiplet bill.

// Now the SAME comparison on a SMALL chip: 100mm2 against 4 x 25mm2
// -> monolithic 20.46 USD   |   chiplet 43.53 USD
// The chiplet costs MORE THAN TWICE as much. Cutting it up was the wrong call.

6. Hands-on: a yield & wafer-cost calculator

Change the die area, defect density, wafer size and number of chiplets needed to watch yield and cost move directly — try raising the monolithic die area to see how fast yield collapses:

Summary

• ✅ Moore's law slowed because of genuine physical limits (quantum tunnelling below 3nm, dark silicon) — but CPU performance still rises through microarchitecture and packaging, not shrinking alone.
• ✅ Chiplets split a big die into several small ones on an interposer — a defective die ruins ONLY itself, rather than the whole system as in a monolithic design.
• ✅ 3D IC + TSVs stack silicon vertically for more capacity and bandwidth — at the cost of cooling the lower layers.
• ✅ Verified: a 600mm² die gives only 90 per wafer at 56.55% yield; a 150mm² chiplet gives 416 per wafer at 86.23%. Monolithic cost ~196.49 USD against 4 chiplets ~111.51 USD — 43% cheaper.
• ✅ Pitfall: that saving does not yet include packaging or per-chiplet testing.
• ✅ Dennard scaling (power density) broke around 2006, BEFORE Moore's law — that is the real reason clocks stalled, the industry moved to many cores, and dark silicon appeared.
• ✅ Verified: a chiplet package is NUMA in miniature — 30% of accesses crossing a die costs 1.9×, while partitioning down to 5% costs only 1.15×. Same hardware, different boundary placement.
• ✅ Verified: the real chiplet saving is 29%, not 43% — the 43% counts silicon only, ignoring the interposer, per-die testing (known-good die) and assembly risk; packaging is 19.5% of the chiplet bill.
• ✅ Verified, and a reversal: for a 100mm² chip, chiplets cost MORE THAN TWICE as much as monolithic (43.53 against 20.46 USD). Chiplets only win when the die is big enough that yield is already bad.

This whole lesson is the story of wringing out what silicon has left: when you cannot shrink it, cut it up; when you cannot cut it up further, stack it. But every one of those keeps one founding assumption — that the unit of computation is a bit, holding only 0 or 1. The very quantum tunnelling that is ruining transistors in section 1 is what another approach to computing takes as its raw material rather than treating as a defect. Lesson 12 closes the series with that approach.

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