Computer Architecture: From Logic Gates to Quantum Computers
Exploring computation from the hardware's point of view
Most software engineers treat the CPU as a magic "black box" — something that takes machine code and returns a result a few milliseconds later. But understanding the microarchitecture underneath is exactly what lets you write code that runs at full speed, diagnose hardware-level security flaws such as Spectre, and get large-scale parallel work right on a GPU or a dedicated AI accelerator.
This roadmap is built to carry you from the first grains of silicon (basic logic gates, adder circuits) through the classic Von Neumann model, the lean RISC-V instruction set, the instruction pipeline, the complexities of out-of-order execution, MMU/TLB virtual memory, on to the unified memory architecture of Apple Silicon — and finally into the era of quantum computing.
About this series
Every lesson comes with pipeline clock-grid timing diagrams, explicit quantitative worked examples (PCIe bandwidth, cache AMAT, the CPI cost of branch mispredictions) and an interactive RISC-V pipeline & L1 cache simulator running directly in the browser, so you can type assembly yourself and watch the data move through the machine.
Before you begin
Foundational glossary
Learning these definitions up front makes every lesson that follows much easier to read:
| Term | What it means |
|---|---|
| ISA (Instruction Set Architecture) | The hardware–software interface: which instructions a CPU can execute and which registers are available. |
| ALU (Arithmetic Logic Unit) | The logic block that performs every arithmetic (add/subtract) and logical (AND/OR/XOR) operation in the CPU. |
| Datapath | The set of wires and functional blocks (ALU, RAM, register file) that data travels through during one instruction cycle. |
| Pipeline hazard | A situation that stops the next instruction executing normally on the next clock cycle (data, control and structural hazards). |
| Speculative execution | The CPU guessing which way a branch will go and running the code ahead of time, to keep the pipeline full. |
| AMAT (Average Memory Access Time) | The metric for memory-hierarchy performance, combining hit time with miss penalty multiplied by miss rate. |
| TLB (Translation Lookaside Buffer) | The MMU's dedicated cache, holding recent virtual-to-physical page mappings so that translation is fast. |
| Tomasulo algorithm | The hardware algorithm for scheduling instructions out of order, eliminating hazards and keeping every execution unit busy. |
| UMA (Unified Memory Architecture) | An architecture placing high-speed memory on one shared bus for the CPU, GPU and NPU together, with no data copying between them. |
| SIMD / SIMT | Parallel execution models running a single instruction across many data elements (or threads) at once. |
| Chiplet | A design approach splitting one monolithic silicon die into several separate functional modules, packaged together on an interposer. |
| Qubit | The basic unit of information in a quantum computer, able to be in both the 0 and 1 states at once through superposition. |
The 12-lesson roadmap
Lesson 1: From Logic Gates to the ALU
Boolean algebra and the AND/OR/NOT/XOR gates at bit level. Building half and full adders, then a 4-bit arithmetic logic unit with its status flags (Zero, Sign, Overflow). Demo: an interactive ALU simulator.
Lesson 2: The Von Neumann Architecture & the ISA
Von Neumann against Harvard, the self-modifying-code pitfall, the fetch-decode-execute cycle, and RISC against CISC. Demo: a toy CPU you step through instruction by instruction — hand-written, reusing the ALU from Lesson 1 directly.
Lesson 3: RISC-V Assembly & the Datapath
The real RV32I instruction set (R/I/S-type), translating assembly into 32-bit machine code, and the single-cycle datapath. Demo: type an assembly instruction, watch the bit breakdown and the data path light up through the ALU, register file and memory.
Lesson 4: CPU Pipelining & Data Hazards
How a 5-stage pipeline raises throughput, the formula T=(N+S-1+stall)×tclk, RAW/WAR/WAW hazards, forwarding, and the load-use hazard pitfall. Demo: a T/CPI calculator plus a hazard simulator with forwarding on and off.
Lesson 5: Branch Prediction & the Spectre Vulnerability
Control hazards, 1-bit and 2-bit branch predictors (FSM + BHT), the effective-CPI formula, speculative execution and the Spectre vulnerability. Demo: a 1-bit versus 2-bit predictor simulation plus an effective-CPI calculator.
Lesson 6: Instruction-Level Parallelism & Out-of-Order Execution (Tomasulo)
Gaining performance through superscalar design. Register renaming to eliminate false WAR/WAW dependencies. The classic Tomasulo algorithm: reservation stations, the common data bus, and the reorder buffer committing in order. Demo: an interactive Tomasulo scheduling table.
Lesson 7: The Memory Hierarchy & Cache Architecture
Beating the memory wall with the principle of locality. Cache mapping design (direct-mapped against set-associative) through the index, tag and offset fields. The practical formula for average memory access time (AMAT).
Lesson 8: Virtual Memory & the TLB
Translating virtual addresses to physical ones through paging and multi-level page tables. The MMU/TLB translation accelerator (TLB hit and miss). A real calculation of how large a page table actually gets.
Lesson 9: Apple Silicon & Unified Memory Architecture
The shift from discrete boards to a system on a chip. Scheduling across big and little cores. An analysis of UMA sharing one LPDDR5 memory bus, and a bandwidth comparison of UMA against PCIe Gen 4. Demo: a direct comparison of frame transfer time over PCIe against UMA.
Lesson 10: Hardware Acceleration: GPU, NPU & AMX
Massively parallel matrix processing. Distinguishing the CPU's SIMD from the GPU's SIMT. The tensor-core principle in an NPU and Apple's proprietary AMX matrix coprocessor. Calculating matrix throughput in TFLOPS. Demo: scalar against SIMD against GPU/AMX.
Lesson 11: The End of Moore's Law & Chiplet Packaging
The physical limits of silicon below 3 nm and current leakage caused by quantum tunnelling. Chiplet architecture as a way to raise yield, plus 3D IC packaging and vertical TSV interconnects. Demo: a yield and wafer-cost calculator.
Lesson 12: Expanding Horizons — Quantum Computing Architecture
Moving from the binary bit to the qubit, with quantum superposition and entanglement. The H, CNOT and Pauli quantum gates, and the principles behind Shor's and Grover's algorithms. Demo: an interactive 2-qubit quantum circuit simulator.